National Institute of Technology

Educational Qualifications

B.Tech, JNTU Kakinada, 200
Ph.D, IIT Guwahati, 2016.

Journals

M. Prakash and R. Shaik, "Low-area and high-throughput architecture for an adaptive ﬁlter using distributed arithmetic," IEEE Trans. Circ. Syst. II, Exp. Briefs., vol. 60, no. 11, pp. 781–785, Nov 2013.
M. Prakash, R. Shaik and K. Sagar, "An Efﬁcient Distributed Arithmetic based realization of the Decision Feedback Equalizer," Circ. Sys. and Sig. Process., Springer, vol. 35, issue. 2, pp. 603-618, Feb 2016.
M. S. Prakash, R. Shaik, "DA based approach for the implementation of block adaptive decision feedback equalizer," IET Sig. Process., vol. 10(6), pp. 676-684, Aug 2016.
Mohd Tasleem Khan, Rafi Ahamed Shaik, Surya Prakash M, "Improved convergent distributed arithmetic based low complexity pipelined least-mean-square filter," IET Circ., Dev., Sys., Apr 2018.
M. Surya Prakash, Rafi Ahamed Shaik, "A Distributed Arithmetic Based Realization of Least Mean Square Adaptive Decision Feedback Equalizer Using Offset Binary Coding Scheme", Elsevier Signal Processing, 2021.
P. Kopperundevi, M. Surya Prakash, Rafi Ahamed Shaik, "A High Throughput Hardware Architecture for Deblocking Filter in HEVC", Sig. Process.: Image Comm., vol.100, 2022.
P. Kopperundevi, M. Surya Prakash, "Methods to Develop High Throughput Hardware Architectures for HEVC Deblocking Filter using Mixed Pipelined-Block Processing Techniques" Microelec. Journ., pp. 105413, vol. 123, 2022.

Conferences

M. Surya Prakash and R. Shaik, "High performance architecture for LMS based adaptive ﬁlter using distributed arithmetic," in Int. Conf. Inform. and Comput. Applicat. (ICICA), vol. 24, pp. 18-22, Mar. 2012.
M. Prakash and R. Shaik, "Low complexity hardware architectural design for adaptive decision feedback equalizer using distributed arithmetic," in IEEE Int. Conf. Comput. Syst. and Ind. Informatics (ICCSII), pp. 1-5, Dec. 2012.
M. Surya Prakash and R. Shaik, "A Distributed Arithmetic based Approach for the Implementation of the Sign-LMS Adaptive Filter," in IEEE Int. Conf. on Sig. Process. and Commun. Eng. Syst. (SPACES), pp. 326-330, Jan. 2015.
P. Kopperundevi, M. Surya Prakash, "A Hardware Architecture for Sample Adaptive Offset Filter in HEVC", accepted for publication in IEEE DISCOVER-2021.
P. Kopperundevi and M. Surya Prakash, "Residue adder design for the modulo set {2ⁿ-1, 2ⁿ,2ⁿ⁺¹-1} and its application in DCT architecture for HEVC," accepted for publication in proceedings of VLSI SATA-2022.
P. Kopperundevi and M. Surya Prakash, "Multiplier Design for the Modulo Set {2ⁿ-1, 2ⁿ,2ⁿ⁺¹-1} and its Application in DCT for HEVC," accepted for publication in proceedings of VSPICE-2022.
Vidyamol K. and M. Surya Prakash, "An Improved Dark Channel Prior For Fast Dehazing of Outdoor Images," accepted for publication in proceedings of ICCCNT-2022.

Books (Refereed)

Kopperundevi, P., and Surya Prakash, M., (2021) “An Efficient Hardware Architecture For Deblocking Filter in HEVC”, in chapter in Innovations in Springer Electrical and Electronic Engineering, vol. 661, Jan-2021.

Professional Experience

Research Scholar Electronics and Electrical Engineering IIT Guwahati Central Government 7 years 2009-2016
Ad-hoc Faculty Electronics and Communication Engineering NIT-Andhra Pradesh Central Government 9 months, 20 days July-24th, 2017 to May 14th, 2017
Assistant Professor Electronics and Communication Engineering NIT-Calicut Central Government June-2018 to today

Semester	Course	Year of Study and Branch
Monsoon-2018	ZZ1003D Basic Electrical Sciences	B. Tech Ist year (CSE, CE)
Monsoon-2018	EC3091 Electronic Circuits-II Laboratory	B. Tech IIIrd year (ECE)
Winter-2018	EC2091D Electronic Circuits-I	B. Tech IInd year (ECE)
Winter-2018	EC2093D Electronic Circuits-I laboratory	B. Tech IInd year (ECE)
Monsoon-2019	ZZ1003D Basic Electrical Sciences	B. Tech Ist year (ME, PE)
	EC6402D Digital Signal Processing Algorithms	M. Tech Ist year (ECE) (SP)
	EC2091D Devices and Networks Laboratory	B. Tech IInd year (ECE)
Winter-2019	ZZ1003D Basic Electrical Sciences	B. Tech Ist year (ECE, EEE)
	EC2091D Electronic Circuits-I	B. Tech IInd year (ECE)
	EC2093D Electronic Circuits-I Laboratory	B. Tech IInd year (ECE)
Monsoon-2020	EC6402D Digital Signal Processing Algorithms	M. Tech Ist year (ECE) (SP)
Monsoon-2020	EC3013D Digital Signal Processing	B. Tech IIIrd year (ECE)
Winter-2020	EC2021D Electronic Circuits-I	B. Tech IInd year (ECE)
	EC2093D Electronic Circuits-I Laboratory	B. Tech IInd year (ECE)
	EC3093D Digital Signal Processing Laboratory	B. Tech IIIrd year (ECE)
Monsoon-2021	EC2011D Electric Circuits and Network Theory	B. Tech IInd year (ECE)
Monsoon-2021	EC2093D Devices and Networks Laboratory	B. Tech IInd year (ECE)
Winter-2021	EC2024D Communication Theory and Systems-I	B. Tech IInd year (ECE)
	ZZ1003D Basic Electrical Sciences	B. Tech Ist year (CSED, CED)
	EC3093D Digital Signal Processing Laboratory	B. Tech IIIrd year (ECED)

Year	Title of the Program
2018-19	Faculty Coordinator, ECE-Association (jointly with Dr. Dhanaraj K. J.). Member of the Exam Vigilance Committee of ECED (jointly with Shri. Suresh, Dr. Venu Anand and Dr. V. Sakthivel and Dr. Venu Anand). Member of the B. Tech Project Evaluation Committee for Embedded & VLSI specializations (jointly with Dr. Deepthi P. P. and Shri. Bhuvan B.). Member of the Volunteer Services Committee for 15th Convocation of NIT-Calicut. Member of M. Tech project Evaluation Team for Internship students. Member of Stock Verification Team for Annual Stock Verification 2018-19. Committee Member for Annual Sports Meet-2019 held at NIT-Calicut.
2019-20	Time-table In-Charge for ECED (jointly with Dr. Bindiya T. S.). Member of the Exam Vigilance Committee of ECED (jointly with Dr. Ali C. K., Dr. Venu Anand and Dr. Sudeep P. V.). Member of the B. Tech Project Evaluation Committee for Embedded & VLSI specializations (along with Shri. Raghu C. V. and Shri. Bhuvan B.). Faculty Advisor for the 2019-23 batch of ECE students (jointly with Dr. Praveen Sankaran, Dr. Suja K. J. and Dr. Gopi Krishna S.). Member of the Announcements Committee for Annual Sports Day. Mentor Faculty from ECED for students internship under TEQIP Twinning program (jointly with Dr. Venu Anand). Application Scrutinization Committee member for Ad-hoc Faculty Interviews held during Monsoon-2019.
2020-21	Time-table In-Charge for ECED (jointly with Dr. Bindiya T. S.). Faculty Incharge for Electronic Circuits Lab of ECED. Faculty Advisor for the 2019-23 batch of ECE students (jointly with Dr. Praveen Sankaran, Dr. Suja K. J. and Dr. Gopi Krishna S.). Committee Member for Disposal/Write-Off of unserviceable items. Committee Member for preparation of Self-Assessment Report (SAR) for MTech Telecommunications specialization. Member of the General Arrangements Committee for National Board of Accreditation Work for Telecommunications Specialization.

S. No.	Title of the Program	Venue	Duration
1.	TEQIP sponsored FDP on “ARM based Embedded System Development”	ECED, NIT-Calicut.	7 days (17/06/2018 - 23/06/2018).
2.	Workshop on Outcome Based Education & Institutional Academic Quality Assurance	ECED, NIT-Calicut	1 day (13/12/2018)
3.	TEQIP sponsored FDP on “Advanced Pedagogy Training Programme”	Teaching Learning Centre, IIT Madras.	3 days (21/03/2019 - 23/03/2019).
4.	Expert Talk on Signal Processing in FDP on “Research Trends in Multimedia and Multirate Signal Processing” (RTMMSP’19)	ECED, NIT-Calicut, (By Prof. Sivaji Chakravorti)	6 days (24/06/2019 - 29/06/2019)
5.	TEQIP sponsored Productivity Enhancement Program	NIT-Calicut	4 days (16/07/2019 - 19/07/2019).
6.	Expert Talk on “Control Path Design for Digital SOCs - using Embedded Processors”	ECED, NIT-Calicut, (By Mathews John)	08/08/2019
7.	TEQIP sponsored course on Digital Transformation in Teaching and Learning Process	IIT Bombay (Online)	2 weeks (06/04/2020 - 22/04/2020).
8.	Training for Xilinx Artix-7 AC701 Evaluation Kit Usage	NIT-Calicut (Online)	22nd June, 2020
9.	Two Hour Professional Workshop on “Prior-Art Searching with Google Patents”	Turnip Innovations, Mumbai (Online)	05/09/2020
10.	30-Hour Live Online Instructor-led Training FDP on "Applied Machine Learning, AI & Its Applications Using Python"	Eduxlabs in association with E-Cell, IIT Hyderabad	1st June, 2021 to 13th June, 2021

S. No.	Title of the Program	Venue	Duration
1.	Self Sponsored Five-Day Online Short Term Training Program (STTP) on “VLSI Architectures for Digital Signal Processing Systems”	NIT-Calicut (Online, jointly with Dr. Ashutosh Mishra)	5 days (14th June, 2021 - 18th June, 2021)

. No.	Title of the Talk/Lecture and Program Details	Venue	Duration
1.	VLSI Digital Signal Processing in FDP on Research Trends in Multimedia and Multirate Signal Processing (RTMMSP’19)	Organized by Dr. Sakthivel, ECED, NIT-Calicut	6 days (24/06/2019 - 29/06/2019)
2.	Lecture on Introduction to VHDL/Verilog Design for Logic Circuits	Organized by GEC Kozhikode under Visiting Faculty Scheme	1 day - 2 Hours (13th December, 2020 10:00AM)
3.	VLSI Digital Signal Processing Systems in STTP on VLSI Architectures for Digital Signal Processing Systems (VADSPS-21)	Organized by Self (along with Dr. Ashutosh)	1 day - 1.25 Hours (14th June, 2021, 11:15AM - 12:30PM)
4.	VLSI Digital Signal Processing Systems in STTP on VLSI Architectures for Digital Signal Processing Systems (VADSPS-21)	Organized by Self (along with Dr. Ashutosh)	1 day - 1.25 Hours (16th June, 2021, 09:30AM - 10:45AM)
5.	VLSI Digital Signal Processing Systems in STTP on VLSI Architectures for Digital Signal Processing Systems (VADSPS-21)	Organized by Self (along with Dr. Ashutosh)	1 day - 1.25 Hours (18th June, 2021, 11:15AM - 12:30PM)
6.	Lecture on High Throughput Architecture for LMS Adaptive Filter Using Distributed Arithmetic in International Conference on Advances in Signal Processing and Communications (NEC-ICASPC-2K21)	Organized by Narasaraopeta Engineering College, A. P.	1 day - 1 Hour (24th July, 2021, 10:00AM - 11:00AM)

S. No.	Title of the Program	Type of Event	Role	Venue	Duration
1.	VLSI Design and Test (VDAT-2020)	Conference	Reviewer	IIT Bhubaneswar	6 days (24/06/2020 - 29/06/2020)
2.	Seventh IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON 2020)	Conference	Reviewer	MNIT Allahabad	3 days (27/11/2020 - 29/11/2020)
3.	Endsemester Exam at Sri Vishnu College of Engineering, A. P.	Exam	Question Paper Setter for Network Theory Course	Sri Vishnu College of Engineering, A. P.	-
4.	National Conference on Advances in Computing Communications Signals Energy and Technology (ACCSET 2021)	Conference	Reviewer	College of Engineering Vadakara	2 days (26/05/2021 - 27/05/2021)
5.	Endsemester Exam at Sri Vishnu College of Engineering, A. P.	Exam	Question Paper Setter for Digital Logic Design	Sri Vishnu College of Engineering, A. P.	-

B. Tech:

S. No.	Title of the Project	Program and Nature of Project	Name and Roll No. of Student	Year
1.	Wireless Electrocardiogram	B. Tech (Mini project)	Radhika R Kurup (B160089EC), Syeda Mahin (B160820EC), Mishab I (B160773EC), Radhul Dev M (B160353EC), Mahanti Sandhyana (B160696EC)	2018-19
2.	Fire Detection and Smart Alerting System	B. Tech (Mini project)	Dunna Akhila (B160694EC), Kanchustambham Satya Sai Pavan Kumar (B160622EC), Ladi Vinod Kumar (B160872EC), Karri Anjana Lakshmi (B160659EC)	2018-19
3.	Indoor Positioning System (jointly with Smt. Lyla B. Das)	B. Tech (Major Project)	Abhay Chandran (B150868EC), A. Yashwanth Sai (B150855EC), C. Vamsi Narayana reddy (B150530EC), D. Manoj (B150624EC), K. Rahul Chowdary (B150713EC)	2018-2019
4.	Hardware Implementation of LeNet-5 Architecture for Convolutional Neural Networks (jointly with Dr. Dhanaraj K. J.)	B. Tech (Major Project)	Manish Murali C (B150586EC), N Srinu (B150998EC), Punya S M (B150178EC), Sandeep J Nair (B150910EC), V Praneesha (B150786EC)	2018-2019
5.	FPGA Implementation of DTMF Signal Detection and Its Piano Application	B. Tech (Major Project)	Kota Sri Navya (B160454EC), Nandipati Anu Deepthika (B160892EC), Sri Ramya Movva (B160130EC), Dunna Akhila (B160694EC), Bhukya Soumya Mishra (B160410EC)	2019-2020
6.	Scientific Calculator Application using CORDIC based implementation of transcendental functions	B. Tech (Major Project)	Polasani Mahesh (B170764EC), Konka Sahith Kumar (B170609EC), Bathula Manikanta Reddy (B170825EC), Bollepalli Laxmi Ram Gopal Raju (B170238EC)	2020-21
7.	Android Controlled Robot	B. Tech (Major Project)	Vikash Kumar (B170395EC), Radheshyam Dhabas (B170768EC), Manish Kumar (B170209EC), Kuldeep Khorwal (B170361EC)	2020-21
8	Development of Automated Grafting Setup Among Solanaceae species of Vegetable (jointly with Dr. A. P. Sudheer, Dr. Maneesh Chandra, Dr. Teja Reddy Vakamalla)	B. Tech (Major Project - Interdepartmental)	Tarala Trilokesh (B190367EC), Abel C Dixon (B190257EP), Ajin J (B190175CH), Devaiah John (B190698EP)	2022-23 (Ongoing)
9	Music Recommendation Based on Facial Emotion Using Machine Learning	B. Tech (Major Project)	Bakka Madhuri (B190124EC), Bana Sreeteja (B191185EC), Chanda Vamsi Vardhan (B191231EC), Kandula V S Madhuri (B190722EC)	2022-23 (Ongoing)
10.	Face Detection and Recognition in Images Using Deep Learning	B. tech (Major Project)	Karalapati Geetha Ashish Sai (B190269EC), Jadpod Pradeep Kumar (B191161EC), Anakampalli Pavan Tej (B191243EC), B. Abhishek (B190444EC), K Leela Krishna Naga Sai (B190755EC)	2022-23 (Ongoing)

M. Tech:

S. No.	Title of the Project	Program and Nature of Project	Name and Roll No. of Student	Year
1.	Hardware Implementation of Distributed Arithmetic Based Adaptive Filter	M. Tech, VLSI (Major Project)	Inturi Gopichand (M180118EC)	2019-2020
2.	PNP Analysis on Next Generation CPU Cores: Maximizing Performance for a given Power Budget (jointly with T. Venkateswara Rao)	M. Tech, VLSI (Major Project) (Internship at Intel, Bangalore)	Avika Tyagi (M180231EC)	2019-2020
3.	Analysis of Formal Methods to Achieve Bug Free Design (jointly with Vikranth Pai)	M. Tech, VLSI (Internship at Intel, Bangalore)	M. Vijay (M180448EC)	2019-2020
4.	Design Verification of different architectural modules/blocks in Nvidia Tegra SoC (jointly with Ramanathan Sambamurthy)	M. Tech (EDT) (Internship at Nvidia, Bangalore)	Shouvik Mukhopadhyay (M180374EC)	2019-2020
5.	A Distributed Arithmetic Based Adaptive Equalizer Implementation on DSP Processor Platform	M. Tech (Telecommunication)	Adarsh D. M. (M180428EC)	2019-20
6.	Hybrid Compile Verification Infrastructure for Light weight Flat Verification and Automatic Regression system for ATE (jointly with Lalit Agarwal, Robin Nanda)	M. Tech (VLSI) (Internship at Nvidia, Bangalore)	Aiswarya K. P. (M190309EC)	2020-21
7.	Regression Test Suite Optimization Using Machine Learning (jointly with Ashish Ganbavale)	M. Tech (VLSI) (Internship at Intel, Bangalore)	Swathy Prakash (M190272EC)	2020-21
8.	Coverage Driven Verification of Different Modules of Time Sensitive Networking IP (jointly with Arpita Sahu)	M. Tech (VLSI) (Internship at Intel, Bangalore)	Monika K. (M190335EC)	2020-21
9.	Hardware Implementation of Orthogonal Matching Pursuit Algorithm for Compressive Sensing Reconstruction	M. Tech (Signal Processing)	M. R. K. S. N. Sai (M190413EC)	2020-21
10.	CORDIC Based Implementation of Transform Model Estimation	M. Tech (VLSI)	Bathula Deepthi (M200474EC)	2021-22 (Ongoing)
11.	Implementation of Music Synthesizer on FPGA Using CORDIC	M. Tech (VLSI)	Kumar Sanu (M200172EC)	2021-22 (Ongoing)
12.	Enhancement of interplay between Dynamic simulations and Formal Property Verification using Automation	M. Tech (VLSI) (Internship at Intel, Bangalore)	Subham Kumar (M200473EC)	2021-22 (Ongoing)
13.	Area and Power Optimization of FIR Filter Banks Using Stochastic Computing	M. Tech (VLSI)	Jeevan Kishore Challa (M210203EC)	2022-23 (Ongoing)
14.	Complex Number Square Root Computation Using Magnitude Estimator Algorithm	M. Tech (VLSI)	Lukka China Balakrishna (M210425EC)	2022-23 (Ongoing)
15.	Performance Analysis of Server SoC Products (jointly with Abraham Shins)	M. Tech (VLSI) (Internship at Intel, Bangalore)	Chelluboyina Abhishek (M210424EC)	2022-23 (Ongoing)
16.	Physical Implementation of GPU Block (jointly with Midhun CK, Mridul Talukdar)	M. Tech (VLSI) (Internship at NVIDIA, Bangalore)	Gullipalli Murali (M210427EC)	2022-23 (Ongoing)

S. No.	Name of the Scholar	Title of Thesis	Research Field	Program	Year of Joining	Status
1.	Kopperundevi P. (B180012EC)	Design of Hardware Architecture for Deblocking Filter in HEVC	VLSI for Multimedia	Regular	2018 (July)	Ongoing (Completed Open Presentation)
2.	Vidyamol K. (P200078EC)	VLSI for ML/Communications	VLSI for ML	Part-time	2021 (January)	Ongoing
3.	Naveen Jones (P210130EC)		VLSI Signal Processing	Full-time	2022 (January)	Ongoing
4.	Mohan Rao (P220124EC)		VLSI Signal Processing	Full-time	2022 (July)	Ongoing

S. No.	Grant	Title of the project	Funding Agency/Institute	Duration	Status
1.	Faculty Research Seed Grant-2019 (FRG-2019)	Design and Implementation of Distributed Arithmetic Based Adaptive Equalizers for Wireless Communications	NIT-Calicut	2 years (2019-21)	Ongoing

Year	Title of the Program
2015 - today	Working as Reviewer for Springer Circuits, Systems and Signal Processing Journal.
2015-16	Worked as Reviewer for Twenty Second National Conference on Communications (NCC-2016) held at IIT Guwahati from 04/03/2016 to 06/03/2016.
2017-18	Worked as Reviewer for Twenty Fourth National Conference on Communications (NCC-2018) held at IIT Hyderabad from 25/02/2018 to 28/02/2018.
2018-19	Participated in All India Inter NIT Tournament (Faculty & Staff) held in December-2018 at NIT-Goa. Accompanied 2016-20 batch of students for Industrial Visit (National Institute of Oceanography).
2019-20	Worked as Micro-observer for counting duty of Indian Loksabha Elections - 2019. Participated in TEQIP-III sponsored One Day Workshop on Basic Life Support - First Responder Training held at NIT-Calicut. Participated in All India Inter NIT Faculty and Staff Cricket Tournament held in December-2019 at VNIT-Nagpur.
2020-21	Unofficially Guided two MCA Students in developing a software application for Subject Allocation

S. No.	Degree	University/Institute	Year
1.	Vice Election Officer for Students Gymkhana Elections 2012-13	IIT Guwahati	2012-13
2.	Warden for Boys Hostel	NIT-Andhra Pradesh	2017-18
3.	Faculty Incharge for Institute Internet Connectivity	NIT-Andhra Pradesh	2017-18
4.	Faculty Advisor in the department of ECE	NIT-Andhra Pradesh	2017-18
5.	Head of the Disciplinary Committee of the Institute	NIT-Andhra Pradesh	2017-18

Memberships:

1. Member, IEEE.

Biology, Consciousness Studies, Spiritual Science.

Snow Effect added to NITC admin building before and after:

Rendered 3D model of NITC ECED Office room:

DEPARTMENTS

Dr. M. Surya Prakash

Dr. M. Surya Prakash

DEPARTMENTS

Dr. M. Surya Prakash

Dr. M. Surya Prakash

Educational Qualifications

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