• Anuja George, Jayakumar E.P., "Hardware-Efficient FrWF-based Architecture for Joint Image Dehazing and Denoising Framework for Visual Sensors", in Journal of Real-Time Image Processing, (2024).
• Siva, M.V., Jayakumar, E.P. "Weighted edge-based low-cost artifacts-free high-quality VLSI implementation for demosaicking", in Journal of Real-Time Image Processing, 21, 180 (2024). https://doi.org/10.1007/s11554-024-01556-z  (https://github.com/Siva0451/Demosaicking).
• Siva, M.V., Jayakumar, E.P. "HSMF: hardware-efficient single-stage feedback mean filter for high-density salt-and-pepper noise removal", in Journal of Real-Time Image Processing, 21, 99 (2024). https://doi.org/10.1007/s11554-024-01475-z (https://github.com/Siva0451/HSMF-Code).
• Arathi Sankar P., Jayakumar E.P., "Edge preserving infrared and visible image fusion with three layer decomposition based on multi-level co-occurrence filtering", in Journal of Infrared Physics & Technology, vol. 139, 105336 (2024), https://doi.org/10.1016/j.infrared.2024.105336.
• Arathi Sankar P, Jayakumar E.P., "Fusion of near-infrared and visible light images under hazy environment using multiplicative dark channel prior", in Journal of Multimedia Tools and Applications (2024). https://doi.org/10.1007/s11042-024-18995-2
• Anuja George, Jayakumar E.P., "Design and Implementation of Hardware-Efficient Architecture for Saturation-based Image Dehazing Algorithm", in Journal of Real-Time Image Processing, 20, 102 (2023), https://doi.org/10.1007/s11554-023-01356-x.
• Anuja George, Jayakumar E.P. "Hardware-Efficient DWT Architecture for Image Processing in Visual Sensors Networks", in IEEE Sensors Journal. vol. 23, no. 5, pp. 5382-5390, 1 March, 2023, doi:10.1109/JSEN.2023.3235371.
• Midde, V.S., Jayakumar, E.P. "Low-cost low-power approximated VLSI architecture for high-quality image scaling in mobile devices", in Journal of Real-Time Image Processing, 20, 11 (2023). https://doi.org/10.1007/s11554-023-01282-y
• Jayakumar, E. P. and P. S. Sathidevi, ”An Integrated Acoustic Echo and Noise Cancellation System using Cross-band Adaptive Filters and Wavelet Thresholding of Multitaper Spectrum”, International Journal of Applied Acoustics (Elsevier), vol.141, pp. 9-18, 2018.
• P. V. Muhammed Shifas, Jayakumar E. P. and P.S. Sathidevi, ”Robust Acoustic Echo Suppression in Modulation Domain,” in Progress in Intelligent Computing Techniques: Theory, Practice, and Applications, Singapore, Springer Nature Singapore Pte Ltd., 2018, pp. 527-537.
• Jayakumar E. P., P. V. Muhammed Shifas, and P. S. Sathidevi, ”Integrated acoustic echo and noise suppression inmodulation domain,” International Journal of Speech Technology (Springer), vol.19, no.3, pp. 611-621, 2016.
• Jayakumar E. P. and P. S. Sathidevi, ”Speech Enhancement Based on Noise Type and Wavelet Thresholding the Multitaper Spectrum,” in Advances in Machine Learning and Signal Processing, Lecture Notes in Electrical Engineering series, Switzerland, Springer International Publishing, 2016, pp. 187-200.

• George Joseph, Jayakumar E.P., "Quantized Neural Network Architecture for Hardware Efficient Real-Time 4K Image Super-Resolution", IEEE 28th International Symposium on VLSI Design and Test (VDAT), Vellore, India, pp. 1-5, 2024. doi: 10.1109/VDAT63601.2024.10705704. 
• Arathi Sankar P, Jayakumar EP, "Infrared and Visible Image Registration Based on Enhanced Whale Optimization Algorithm." In 2023 Annual International Conference on Emerging Research Areas: International Conference on Intelligent Systems (AICERA/ICIS), pp. 1-5. IEEE, 2023.
• Pranshul Goel, Siva M.V. and Jayakumar EP, "Hardware Efficient Edge-Detection Based Color Filter Array Interpolation for Industrial Cameras." In 2023 IEEE Industrial Electronics and Applications Conference (IEACon) (pp. 86-91). IEEE. 2023.
• Siva MV, Jayakumar E P “An Inaccurate Median Filter Architecture for Salt and Pepper Noise Removal”, In 3rd IEEE International Conference on VLSI Systems, Architecture, Technology and Applications (VLSI SATA-2022), (pp.  1-5), 2022.
• Das LB, Jayakumar EP, Jagadanand G, Meghana O, Satheesh P, Sriharsha R, Prasanna VL, Aswini V. “Design of a Personal Digital Assistant for the Visually Challenged”, In 2022 IEEE International Conference on Industry 4.0, Artificial Intelligence, and Communications Technology (IAICT) 2022 Jul 28 (pp. 15-21).
• Kartheek P, Jayakumar EP. “Hardware Architecture for Adaptive Edge-Directed Interpolation Algorithm”, In 2022 IEEE International Conference on Industry 4.0, Artificial Intelligence, and Communications Technology (IAICT) 2022 Jul 28 (pp. 1-7).
• Narendiran S, Jayakumar E P., “An Efficient Modified Distributed Arithmetic Architecture Suitable for FIR Filter”, In 2021 IEEE Sixth International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) 2021 Mar 25 (pp. 89-93).
• Siva MV, Jayakumar E P, “Approximated algorithm and low cost VLSI architecture for edge enhanced image scaling”, In 2020 IEEE International Conference on Industry 4.0, Artificial Intelligence, and Communications Technology (IAICT) 2020 Jul 7 (pp. 125-130).
• Siva MV, Jayakumar EP, ‘A Low Cost High Performance VLSI Architecture for Image Scaling in Multimedia Applications”, In 2020 7th International Conference on Signal Processing and Integrated Networks (SPIN) 2020 Feb 27 (pp. 278-283).
• Ramanathan SG, Kumar BP, Ananda CM, Jayakumar EP, “Design of graphics processing framework on FPGA,” in IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2016), 20-21 May 2016 at Sri Venkateshwara College of Engineering, Bengaluru, India, (pp. 387-391).
• Dinesh MV, Ananda CM, Kumar BP, Jayakumar EP, “Design and implementation of fiber channel based high speed receiver protocol for avionics on FPGA,” in IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2016), 20-21 May 2016 at Sri Venkateshwara College of Engineering, Bengaluru, India, (pp. 1195-1200).
• Narapureddy P, Ananda CM, Kumar BP, Jayakumar EP, “Design and implementation of fiber channel based high speed serial transmitter for data protocol on FPGA,” in IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT-2016), 20-21 May 2016 at Sri Venkateshwara College of Engineering, Bengaluru, India, (pp. 926-931).

1. Design of Digital Systems

2. Reconfigurable System-on-Chip

3. Verification of VLSI Systems

4. Modelling and Testing of Digital Systems

Ongoing

ARATHI SANKAR P (Full Time)

MIDDE VENKATA SIVA (Full Time)

ANJU GEORGE (Part-time)

NAVYA M.V. (Full Time - QIP)

Completed

ANUJA GEORGE (Full Time - QIP)

Thesis Title: Design and Implementation of Hardware-Efficient VLSI Architectures for Joint Dehazing and Denoising Framework in Visual Sensor Networks

Date of Viva-voce Examination: 17-04-2024