• M. Cabbia, S. Fregonese, M. Deng, A. Curutchet, C. Yadav, D. C´eli, M. D. Matos, and T. Zimmer, “Meander-Type Lines: An Innovative Design for On-Wafer TRL Calibration for mmW and sub-mmW Frequencies Measurements”, IEEE Transactions on Terahertz Science and Technology, vol. 11, no. 4, pp. 367 - 374, July 2021.
• C. Yadav, M. Deng, S. Fregonese, M. Cabbia, M. D. Matos, and T. Zimmer, “Investigation of Variations in on-Si On-wafer TRL Calibration in sub-THz”, in IEEE Transactions on Semiconductor Manufacturing, vol. 34, no. 2, pp. 145 - 152, May 2021. 
• M. Deng, C. Mukherjee, C. Yadav, S. Fregonese, T. Zimmer, M. D. Matos, W. Quan, A. Arabhavi, C. Bolognesi, X. Wen, M. Luisier, C. Raya, B. Ardouin and C. Maneux, “Design of On-wafer TRL Calibration Kit for InP Technologies Characterization up to 500 GHz”, in IEEE Transactions on Electron Devices, vol. 67, no. 12, pp. 5441-5447, Dec. 2020.
• M. Cabbia, C. Yadav, M. Deng, S. Fregonese, M. D. Matos, and T. Zimmer, “Silicon Test Structures Design for Sub-THz and THz Measurements”, in IEEE Transactions on Electron Devices, vol. 67, no. 12, pp. 5639-5645, Dec. 2020.
• S. Fregonese, M. Deng, M. Cabbia, C. Yadav, M. D. Matos, and T. Zimmer, “THz Characterization and Modeling of SiGe HBTs: Review (invited)”, in IEEE Journal of the Electron Devices Society (J-EDS), vol. 8, pp. 1363-1372, 2020.
• S. Fregonese, M. Cabbia, C. Yadav, M. Deng, R. R. Panda, M. D. Matos, A. Chakravorty, and T. Zimmer, “Analysis of high Frequency Measurement of Transistors along with Electromagnetic and SPICE co-Simulation”, in IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 4770 - 4778, Nov. 2020.
• S. A. Ahsan, S. K. Singh, C. Yadav, E. G. Mar´ın, A. Kloes and M. Schwarz, “A Comprehensive Physics-Based Current-Voltage SPICE Compact Model for 2-D-Material-Based Top-Contact Bottom-Gated Schottky-Barrier FETs”, in  IEEE Transactions on Electron Devices, vol. 67, no. 11, pp. 5188 - 5195, Nov. 2020.
• C. Yadav, M. Deng, S. Fregonese, M. Cabbia, M. D. Matos, B. Plano, and T. Zimmer, “Importance and Requirement of Frequency band specific RF probes EM Models in sub-THz and THz Measurements up to 500 GHz” in  IEEE Transactions on Terahertz Science and Technology, vol. 10, no. 5, pp. 558-563, Sept. 2020.
• K. Nandan, C. Yadav, P. Rastogi, A. T.-Lopez, A. M.-Sanchez, E. G. Marin, F. G. Ruiz, S. Bhowmick, and Y. S. Chauhan, “Compact Modeling of Multi-layered MoS2 FETs including Negative Capacitance Effect”, in IEEE Journal of the Electron Devices Society (J-EDS), vol. 8, pp. 1177-1183, 2020.
• S. Fregonese, M. Deng, M. D. Matos, C. Yadav, S. Joly, B. Plano, C. Raya, B. Ardouin and T. Zimmer, “Comparison of On-wafer TRL calibration to ISS SOLT calibration with Open-Short De-embedding up to 500 GHz", in IEEE Transactions on Terahertz Science and Technology, vol. 9, no. 1, pp. 89 - 97, Jan. 2019.
• C. Yadav, P. Rastogi, T. Zimmer and Y. S. Chauhan, "Charge-Based Modeling of Transition Metal Dichalcogenide Transistors Including Ambipolar, Trapping, and Negative Capacitance Effects," in IEEE Transactions on Electron Devices, vol. 65, no. 10, pp. 4202-4208, Oct. 2018.
• M. D. Ganeriwala, C. Yadav, F. G. Ruiz, E. G. Marin, Y. S. Chauhan and N. R. Mohapatra, "Modeling of Quantum Confinement and Capacitance in III–V Gate-All-Around 1-D Transistors," in IEEE Transactions on Electron Devices, vol. 64, no. 12, pp. 4889-4896, Dec. 2017.
• P. Jain, P. Rastogi, C. Yadav, A. Agarwal, and Y. S. Chauhan, “Band-to-Band Tunneling in Г valley for Ge Source Lateral Tunnel Field Effect Transistor: Thickness scaling", in Journal of Applied Physics, vol. 122, pp. 014502, 2017.
• C. Yadav, M. D. Ganeriwala, N. R. Mohapatra, A. Agarwal and Y. S. Chauhan, "Compact Modeling of Gate Capacitance in III–V Channel Quadruple-Gate FETs," in IEEE Transactions on Nanotechnology, vol. 16, no. 4, pp. 703-710, July 2017.
• P. Jain, C. Yadav, A. Agarwal, Y. S, Chauhan, “Surface Potential based Modeling of Charge, Current, and Capacitances in DGTFET including Mobile Channel Charge and Ambipolar Behavior” in Solid-State Electronics, vol. 134, pp. 74-81, 2017.

• C. Yadav, M. Agrawal, A. Agarwal and Y. S. Chauhan, "Compact Modeling of Charge, Capacitance, and Drain Current in III–V Channel Double Gate FETs," in IEEE Transactions on Nanotechnology, vol. 16, no. 2, pp. 347-354, March 2017.
• C. Yadav, A. Agarwal and Y. S. Chauhan, "Compact Modeling of Transition Metal Dichalcogenide based Thin body Transistors and Circuit Validation," in IEEE Transactions on Electron Devices, vol. 64, no. 3, pp. 1261-1268, March 2017.
• M. D. Ganeriwala, C. Yadav, N. R. Mohapatra, S. Khandelwal, C. Hu and Y. S. Chauhan, "Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs," in IEEE Journal of the Electron Devices Society, vol. 4, no. 6, pp. 396-401, Nov. 2016.
• C. Yadav, J. P. Duarte, S. Khandelwal, A. Agarwal, C. Hu and Y. S. Chauhan, "Capacitance Modeling in III–V FinFETs," in IEEE Transactions on Electron Devices, vol. 62, no. 11, pp. 3892-3897, Nov. 2015.
• H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model," in IEEE Journal of the Electron Devices Society, vol. 3, no. 3, pp. 240-243, May 2015.
• P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu, and Y. S. Chauhan, “Modeling the impact of substrate depletion in FDSOI MOSFETs,” in Solid-State Electronics, vol. 104, pp. 6-11, 2015.
• C. Yadav, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. S. Chauhan and C. Hu, "Modeling of GaN-Based Normally-Off FinFET," in IEEE Electron Device Letters, vol. 35, no. 6, pp. 612-614, June 2014.
• S. Khandelwal, C. Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J. C. Dejaeger, N. Defrance and T. A. Fjeldly, "Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design," in IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3216-3222, Oct. 2013.

• M. Cabbia, S. Fregonese, C. Yadav, and T. Zimmer, “TRL-calibration Standards with Emphasis on Crosstalk Reduction”, in 14^th Global Symposium on Millimeter-Waves & Terahertz (GSMM), Seoul, Korea, May 2022.
• C. Yadav, M. Cabbia, S. Fregonese, M. Deng, M. D. Matos, B. Plano, and T. Zimmer, “S-Parameter Measurement and EM Simulation of Electronic Devices towards THz frequency range”, in IEEE 34^th International Conference on Microelectronic Test Structures (ICMTS), Texas, USA, March 2022.
• C. Yadav, M. Cabbia, S. Fregonese, M. Deng, M. D. Matos, B. Plano, and T. Zimmer, “Guideline of Test Structures placement for on-Wafer Measurement of Electron Devices in sub-THz”, in IEEE MTT-S International Microwave Symposium (IMS), Atlanta, USA, June 2021.
• M. Cabbia, M. Deng, S. Fregonese, C. Yadav, A. Curutchet, M. D. Matos, D. C´eli, T. Zimmer, “Meander-Type Transmission Line Design for On-Wafer TRL Calibration up to 330 GHz,” in 50^th European Microwave Conference (EuMC), Utrecht, Netherlands, Jan. 2021, pp. 979-982.
• S. Moparthi, C. Yadav, G. Krishna, and P. K. Tiwari, “Machine Learning based Device Simulation using Multi-Variable Non-linear Regression to Assess the Impact of Device Parameter Variability on Threshold Voltage of Double Gate-All-Around (DGAA) MOSFET”, in 2^nd IEEE Int. Conference on Circuits and Systems (IEEE ICCS), Chengdu, China, Dec. 2020, pp. 64-67. 
• S. R. Panda, M. Cabbia, M. Deng, S. Fregonese, C. Yadav, A. Chakravorty, T. Zimmer, "SiGe HBT Device Characterization up-to 500 GHz: Procedure and Layout Improvement of Calibration Standards," 2020 5th IEEE International Conference on Emerging Electronics (ICEE), 2020, pp. 1-4
• K. Nandan, C. Yadav, P. Rastogi, A. T.-Lopez, A. M.-Sanchez, E. G. Marin, F. G. Ruiz, S. Bhowmick, Y. S. Chauhan, "Compact Modeling of Surface Potential and Drain Current in Multi-layered MoS2 FETs," 4^th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Penang, Malaysia, 2020, pp. 1-4.
• C. Yadav, S. Fregonese, M. Deng, M. Cabbia, M. D. Matos, and T. Zimmer, “On the Variation in Short-Open De-embedded S-parameter Measurement of SiGe HBT up to 500 GHz", in 12^th German Microwave Conference (GeMiC), Stuttgart, Germany, March 2019, pp. 264 - 267.
• C. Yadav, S. Fregonese, M. Deng, M. Cabbia, M. D. Matos, M. Jaoul and T. Zimmer, “Analysis of Test Structure design Induced Variation in on Si On-wafer TRL calibration in sub-THz", in 32^nd IEEE Int. Conference on Microelectronics test Structures, Fukuoka, Japan, March 2019, pp. 132 - 136.
• Y. S. Chauhan, C. Yadav, A. Dasgupta and P. Rastogi, "Atomistic Simulation and Compact Modeling of Atomically Thin Transistors," 2018 10th International Conference on Electrical and Computer Engineering (ICECE), Dhaka, Bangladesh, 2018, pp. 1-6.
• C. Yadav, M. Deng, S. Fregonese, M. De Matos, B. Plano and T. Zimmer, "Impact of on-Silicon De-Embedding Test Structures and RF Probes Design in the Sub-THz Range," 48^th European Microwave Conference (EuMC), Madrid, Spain, Sept. 2018, pp. 21-24.
• C. Yadav, M. Deng, M. D. Matos, S. Fregonese, and T. Zimmer, “Importance of Complete Characterization Setup on On-wafer TRL calibration in sub-THz Range” 3^1st IEEE International Conference on Microelectronic Test Structures (ICMTS), Austin, TX, March 2018, pp. 197-201.
• C. Yadav, A. Dutta, S. Sirohi, T. Ethirajan and Y. S. Chauhan , “Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence” 29^th International Conference on VLSI Design and 2016 15^th International Conference on Embedded Systems (VLSID), Kolkata, Jan. 2016, pp. 328-333.
• C. Yadav, A. Agarwal and Y. S. Chauhan, “Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor” 2^9th International Conference on VLSI Design and 2016 1^5th International Conference on Embedded Systems (VLSID), Kolkata, Jan. 2016, pp. 571-572.
• C. Yadav, P. Kushwaha, H. Agarwal and Y. S. Chauhan,“Threshold voltage modeling of GaN based normally-off tri-gate transistor” 11^th IEEE India Conference (INDICON), Pune, Dec. 2014, pp. 1-4.a

• S. Fregonese, M. Deng, M. Cabbia, C. Yadav, S. R. Panda, T. Zimmer “On wafer small signal characterization beyond 100 GHz for compact model assessment” 49^th European Microwave Conference (EuMC), Paris, France, Sept. 2019.
• M. Cabbia, M. Deng, C. Yadav, S. Fregonese, M. D. Matos, T. Zimmer“Caractérisation RF de transistors bipolaires à hétérojonction SiGe jusqu’à 500 GHz”13^ème Colloque National du GDR SOC², Montpellier, France, 19, 20 et 21 juin 2019.
• C. Yadav, M. Deng, S. Fregonese, M. D. Matos, and T. Zimmer “Measurement issues of on-Silicon de-embedding test structures in the Sub-THz range” 30^th BipAk, Frickenhausen, Germany, Nov. 2018.
• C. Yadav and Y. S. Chauhan, “Modeling of Transition Metal Dichalcogenide Transistors for SPICE Simulation” MOS-AK Workshop, Berkeley, USA, Dec. 2016.
• C. Yadav, A. Agarwal, and Y. S. Chauhan “Compact Modeling of charge Density and Capacitance in III-V channel Double gate FETs” Int. Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
• C. Yadav, A. Agarwal, and Y. S. Chauhan “Effect of Back Bais on Quantum Capacitance in III-V Transistors” SRC TECHCON, Austin, USA, Sep. 2015
• C. Yadav, S Khandelwal and Y. S. Chauhan “Modeling of AlGaN/GaN FinFET” Workshop on Compact Modeling, Washington D.C., USA, June 2014.
• Y. S. Chauhan, P. Kushwaha, S. Khandelwal, C. Yadav, N. Paydavosi, J. P. Duarte and C. Hu  “BSIM-IMG: Compact Model for UTBBSOI MOSFETs” Workshop on Compact Modeling, Washington D.C., USA, June 2014.

1) Compact Modeling and Numerical Simulation: Conventional Si and alternative channel material FETs, High power device GaN HEMT, LDMOS, etc.;

2) Research in sub-THz and THz Frequency Range: Imaging for Biomedical Applications and Material Characterization, Electrical Characterization, Device Modeling, Circuit & System Design

 3) Electronics for Quantum Computing application and Machine Learning application in Semiconductor Device research

Memberships: IEEE Senior Member; Member IEEE Electron Devices Society

Reviewer:

1. Journal: IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Transactions on Terahertz Science and Technology, IEEE Sensors Journal, IEEE Access, Solid-State Electronics, Microelectronics Journal, Applied Physics Letters, Microelectronics Engineering, IETE Technical Review, Springer - Journal of Computational Electronics.

2. Conference: UPCON-2015, TENCON-2016.

If you are interested in working with me, please send your C.V. to me at chandan@nitc.ac.in. I am looking for motivated and interested B.Tech., M.Tech., Ph.D., and PostDoc candidates.  

Scholarships for Ph.D./postDoc Candidates:

PostDoc Candidate: National Post Doctoral Fellowship (N-PDF), webpage link: https://serbonline.in/SERB/npdf

                               : Chief Minister’s Nava Kerala Post Doctoral Fellowships webpage link: Chief Minister's Nava Kerala Post Doctoral Fellowships

Ph.D. Candidate: 1.  JRF-NET exam, webpage: https://www.csirhrdg.res.in/Home/Index/1/Default/1246/60 

https://scholar.google.co.in/citations?hl=en&user=1pZkCAwAAAAJ&view_op=list_works&sortby=pubdate