• K. R. Sreelekha, T. S. Bindiya, "Design of Cost Effective Variable Bandwidth 2D Low-pass, High-pass and Band-pass Filters with Improved Circularity”, Digital signal processing (Elsevier), 2022
• Hareesh V. and Bindiya T. S., "Design of Hardware Efficient Reconfigurable Merged Partial Cosine Modulated Non-uniform Filter Bank Channelizer and its Power Efficient Implementation using a Novel Approximation Algorithm", Circuits, Systems, and Signal Processing (Springer), 2021
• Sreelekha K. R., Bindiya T. S., "Design of Variable Elliptical Filters with Direct Tunability in 2D Domain",  Multidimensional Systems and Signal Processing (Springer), 2021
• Sudharman S, Bindiya T. S., "Design of Recongurable FRM Channelizer using Resource Shared Non-maximally Decimated Masking Filters", Journal of Signal Processing Systems (Springer), 93, 913–922, 2020
• Hareesh V. and Bindiya T. S., "Analysis of Different Rational Decimated Filter Banks Derived From the Same Set of Prototype Filters", IEEE Transactions on Signal Processing, 2020, 68, pp.1923-1936.
• Hareesh V. and Bindiya T. S., "Design of Low-Complex Linear-Phase Non-uniform Filter Bank to Realize Wavelet Approximation of Bark Frequency Partitioning for Real-Time Applications", Circuits, Systems, and Signal Processing (Springer), 2020, pp.1-27.
• Sudharman S, Bindiya T. S., "Design of Power Efficient Variable Bandwidth Non-maximally Decimated FRM Filters for Wideband Channelizer", IEEE Transactions on Circuits and Systems II: Express Briefs. 2019,  66(9), pp. 1597 - 1601
• Sudhi Sudharman, Athul D. Rajan, T. S. Bindiya, "Design of a Power-Efficient Low-Complexity Reconfigurable Non-maximally Decimated Filter Bank for High-Resolution Wideband Channels", Circuits, Systems, and Signal Processing (Springer), 2019, 38(6), pp. 2703-2735.
• Amir A., Bindiya, T. S. and Elizabeth Elias, "Low-complexity implementation of efficient reconfigurable structure for cost-effective hearing aids using fractional interpolation", Computers & Electrical Engineering (Elsevier), 2019, 74, pp.391-412.
• Amir A, J Pragadeeshwaran, T. S. Bindiya, Elizabeth Elias, "Reconfigurable filter bank structures for low complexity digital channelizer using fractional interpolation and MFIR filters with cosine modulation", AEU-International Journal of Electronics and Communications (Elsevier), 2018, 94, pp. 262-276
• Amir A., Bindiya T. S. and Elizabeth Elias, “Design and Implementation of Reconfigurable Filter Bank Structure for Low Complexity Hearing Aids using 2-level Sound Wave Decomposition”, Biomedical Signal Processing and Control (Elsevier), 2018, 43, pp. 96-109
• Bindiya, T. S. and Elizabeth Elias, "Meta-heuristic evolutionary algorithms for the design of optimal multiplier-less recombination filter banks.", Information Sciences (Elsevier), 2016, 339, pp. 31-52
• Bindiya, T. S. and Elizabeth Elias, "Design of FRM-based MDFT filter banks in the canonic signed digit space using modified meta-heuristic algorithms.", International Journal of Signal and Imaging Systems Engineering (Inderscience), 2016, 9(1), pp. 20-37.
• Bindiya T. S. and Elizabeth Elias, “Design of Totally Multiplier-less Sharp Transition Width Tree Structured Filter Banks for Non-uniform Discrete Multitone System", International Journal of Electronics and Communications (Elsevier), 2015 Mar 31; 69(3): 655-65.
• Bindiya T. S. and Elizabeth Elias, “Modified meta-heuristic Algorithms for the Optimal Design of Multiplier-Less Non-uniform Channel Filters”, Circuits, Systems, and Signal Processing (Springer), March 2014, Volume 33, Issue 3, pp. 815-837.
• Bindiya T. S. and Elizabeth Elias, “Meta-heuristic Algorithms for the Design of Multiplier-less Non-Uniform Filter Banks based on Frequency Response Masking”, Soft Computing (Springer), July 2014, Volume18, Issue 8, pp. 1529-1547.
• Bindiya T. S. and Elizabeth Elias, “Design of Multiplier-less Sharp Transition Width Non-Uniform Filter Banks Using Gravitational Search Algorithm”, International Journal of Electronics (Taylor and Francis), 2015 Jan 2;102(1):48-70.

UG Courses

1. VLSI Circuits and Systems
2. Modeling and Testing of Digital Systems
3. Logic Design 
4. Computer Organization and Architecture
5. Network Theory  
6. Signals and Systems
7. Basic Electronics

PG Courses

1. Physical Design Automation 
2. Digital Integrated Circuit Design
3. Digital System Design
4. Low Power VLSI
5. Testing and Verification of VLSI Circuits 
6. DSP System Design
7. Multirate Signal Processing

PhD

Completed - 3

1. Hareesh (Design of Hardware Efficient Rational Decimated Filter Banks Using Partial Cosine Modulation and Sub-Band Merging) (09/12/2016 - 01/06/2022)
2. Sudhi Sudharman, "Design and Synthesis of Reconfigurable-non-maximally Decimated and Maximally Decimated Polyphase Filter Bank Based Structures", 2020 (15/07/2015 - 29/07/2020).
3. Amir A, "Design and Implementation of Fractional Interpolation Based Reconfigurable and Hardware Efficient Digital Filter Structures" (Co-guided with Dr. Elizabeth Elias), 2018. (05/01/2015 - 26/09/2018)

Ongoing - 5

Full Time - 4

1. Sreelekha K. R. (Multidimensional Filters) (08/12/2017 - )
2. Tresa Joseph (Digital VLSI Circuits) (16/12/2019 - )
3. Neeraja P. K. (VLSI implementation of DSP architectures) (Co-guidance with Dr. Raghu C. V.) (28/01/2021 - )
4. Sruthi P. V. (Digital VLSI Circuits) (18/08/2021 - )

 Part Time - 1

1. Rinson Varghese (Multidimensional Filters) (23/12/2022 - )

M. Tech Major Projects

Ongoing - 4

Completed - 39

1. Md Qamar Tabish (Hardware Implementation of Sigmoid Function (2021 - 2022)
2. Sandhya G (Design of Low Complexity Arbitrary Pass-Band Filter Hardware using Newton Structure based Lagrange and Hermite Interpolators) (2021 - 2022)
3. Gangireddy Pallavi (Quality Checks and Timing Convergence in Complex Multi-Million Gate SoC Design, Co-guided with Mr. Karthik Ramanathan, Intel Pvt Ltd) (2021 - 2022)

4. Ramavath Mohan Naik (A Memory Efficient Matrix Transposition Architecture using Pipelining) (2020 - 2021)

5. Suresh Reddy (Intel) (2020 - 2021)
6. A Niranjan (Design of Low Power Approximate Binary Logarithmic Multipliers) (2020 - 2021)
7. Sreegul G. (A Heuristic Approach in the Signed Power of Two Space for The Power and Area EfficientRealization of Digital Filters) (2019 - 2020)
8. Naresh Elukati (Realization of Power Efficient FIR Filters using Hybrid Accurate-Inaccurate Adder/Subtractor Architecture) (2019 - 2020)
9. Sajish Francis (Netlist to GDSII Layout Flow for Graphics Processing Unit Macros in Sub-16nm Technology Regime, Coguided with Mr. Vipin Patel, Engineering Manager, NVIDIA Grpahics Pvt. Ltd.) (2019 - 2020)
10. Ankit Vyas (Variation Immune Sense Amplifier for High Speed Memory Applications, Coguided with Mr. Harsha Bharadwaj, Engineering Manager, NVIDIA Grpahics Pvt. Ltd.) (2019 - 2020)
11. Srinivas (Physical Implementation Of Graphics Processing Unit Blocks Targeting Improved Power Performance Area Specifications, Coguided with Mr. Jayanth Prakash, Engineering Manager, NVIDIA Grpahics Pvt. Ltd.) (2019 - 2020)
12. Raviteja (Block Level Layout Design From Netlist to GDS , Coguided with Mr. Jayanth Prakash, Engineering Manager, NVIDIA Grpahics Pvt. Ltd.) (2019 - 2020)
13. Seerapu Naveen (Functional Verification of Time-Sensitive Networking IP Blocks in Pre-Si Environment, Coguided with Mr. Praveen P., IP Verification Engineer, Intel Technology India Pvt. Ltd.) (2019 - 2020)
14. Nisha Vaishnav (Global Clock Distribution Design for Microprocessor Core with Lowpower and Low Clock Skew Variation, Coguided with Mr. Paresh Udawant, Technical Lead, Intel Technology India Pvt. Ltd.) (2019 - 2020)
15. Manuprasad V. (Implementation of Power and Area Efficient Reconfigurable FIR Filters Using Inexact Adders and Subtractors) (2018 - 2019)
16. Balaraj M. (Fault Injection Framework Deployment to Enable Concurrent Fault Simulations and Diagnostic Coverage Validation, Coguided with Mr. Siva Prasad Kota, Technical Lead, Intel Technology India Pvt. Ltd.) (2018 - 2019)
17. Shivaramakrishna (2018 - 2019)
18. Niyas K. (Performance Analysis of SoC Interconnect Bus Using System C, Coguided with Mr. Raja Jondhle, Project Program Manager, Intel Technology India Private Limited, Bangalore) (2018 - 2019)
19. Ananya Suresh (Power Optimization in High Frequency CPU Core Through Multiple Voltage Domain, Coguided with Mr. Tiju Jacob and Mr. Satish Sethuraman, Intel Technology India Private Limited, Bangalore) (2018 - 2019)
20. Reshma Abraham (Design of Scalable and Configurable IP And IP Collaterals, Coguided with Mr. Sunil Aggarwal, Sr. Logic Design Engineer, Intel Technology India Private Limited, Bangalore) (2018 - 2019)

• Associate Dean (R&C), (February 2022 - Till date)
• Reviewer of IEEE TCAS II, Wiley, Taylor and Francis, Springer Journals
• ECED Time Table in charge (2015 - 2022)
• ECED Purchase Coordinator (2018 - 2022)
• Faculty in charge of Dept. Staff amenities/Seminar Halls/Projectors (2015 - 2016)
• Member of ECED Time Table Committee (2013 - 2015) 
• Member, B Tech major project evaluation committee (2015 - 2018, 2020 Onwards)
• Member, B Tech mini project evaluation committee (2012 - 2015)
• Faculty advisor of 2009 - 2013, 2013 - 2017, 2017 - 2021, 2022 - 2026 ECE B. Tech Batches
• Ladies Hostel Warden (2009 - 2010)