Faculty-In-Charge

Dr. Gopi Krishna Saramekala, Assistant Professor, ECED

Staff-In-Charge

Mr. Sreekanth S, Technical Assistant, ECED

Location and Room No

ECED Block-2, 207

Course

Semester

EC6101E: Design of Digital Systems

Monsoon

EC6131E : Reconfigurable System on chip

Winter

Sl No

Equipments

1

Desktop Computers

2

Workstations

Sl No

Name

1.

FPGA: EK-K7-KC705-G Xilinx Kirtex-7 FPGA KC705 Evaluation Kit

2. 

FPGA: EK-Z7ZC702-G Xilinx Zynq-7000 All Programmable SoC ZC702 Evaluation Kit

3.

FPGA: EK-V7-VC707-G Xilinx Virtex 7FPGA VC707 Evaluation Kit

4.

FPGA: ZedBoard Development Board

Sl No

Name

1.

Silvaco TCAD Omni Bundle and ACD Bundle

List of Experiments

1

Structural level Verilog code of basic combinational circuits like Half Adder, Full Adder,

Multiplexer, Demultiplexer, etc.

2

Dataflow level Verilog code of Multiplexer, Demultiplexer, Decoder and Encoder using

Conditional Operator.

3

Design of a four-bit prime number circuit and structural level Verilog code.

4

Behavioral level Verilog code of flip flops, registers and counters.

5

Structural level Verilog code of N-bit Ripple Carry Adder using parameter and generate.

6

Demonstrate self-checking testbench for 4-bit RCA using files, tasks and functions.

7

Design FSM to detect a pattern in the input bit stream and model it using Verilog code.

8

Design a combination lock FSM with automatic lock feature.

9

Design a vehicle tail lamp controller and demonstrate using FPGA.

10

Design a 4-bit ALU and demonstrate using FPGA.

List of Experiments

1

Control and Observe using VIO and ILA.

2

Use a MicroBlaze Softcore processor on FPGA and write a program to print “Hello World”.

3

Use a MicroBlaze Softcore processor and GPIO IPs to be connected to switches and LEDs. Follow the polling method to read the switch positions and control LED.

4

Implement Exp-3 using the interrupt method.

5

Implement a digital clock.

6

Create the block design with the Zynq processing system and write a C program to print “Hello World” on the serial port.

7

Create the block design with Zynq processing system, DMA and FIFO IP cores in PL. Write a C program to configure the DMA to transfer data between Memory and FIFO.

8

Create the block design with Zynq processing system and write a C program to compute 8-point Fast Fourier Transform and print results on the serial port. 

9

Create the block design with Zynq processing system, DMA and FFT IP cores in PL. Demonstrate DMA configuration to transfer input data to FFT IP core and transfer back the computed FFT output. 

10

Create the block design with Zynq processing system, DMA, FFT and BRAM IP cores in PL. Demonstrate DMA configuration to transfer input data to FFT IP core and transfer back the computed FFT output to BRAM.